1. Field of the Invention
The present invention generally relates to timing analysis tools. More particularly, the present invention relates to an improved method and system for the calculation of quantities to perform clock gating tests at gating devices during an integrated circuit design.
2. Description of the Related Art
Integrated circuit (IC) manufacturers have continuously sought to build smaller and more efficient integrated circuit chips that contain an increasing number of devices. Because the designing of IC chips is so complex, a programmed data processor is essential. The most common method of designing logic circuits for placement on IC chips is done with the use of computer systems and software that use computer-aided design (CAD) tools. Particular components that allow for an efficient design, checking and testing of very large scale integrated circuits (VLSI) are referred to as logic synthesis and physical design tools.
A logic synthesis tool takes as input a functional description of a logic circuit, typically written in a language such as VHDL, and then converts it into a technology level description. The circuits in this technology level description are then placed and the wires interconnecting them are routed by physical design tools, producing a set layout level representation that a chip foundry can use to actually build the chip. The output of the logic synthesis tool is referred to as a net list, which is actually a list of cells from a technology library and the necessary interconnections between the cells. The output of the physical design tools includes a xe2x80x9cplacementxe2x80x9d (the assignment to each circuit in the net list of a physical location on the chip), and a xe2x80x9croutingxe2x80x9d (the assignment to each net in the net list a set of wire segments which implement the interconnections defined by the net), collectively referred to as the physical layout of the chip. Thus, the output of the electronic design automation system may be regarded as a template for the fabrication of the physical embodiment of the integrated circuit.
While generating the netlist and physical layout of the IC, these CAD tools must meet the timing constraints that are specified as part of the design. Timing tools, such as IBM""s xe2x80x9cEinsTimerxe2x80x9d tool system, provide timing analysis of circuit net lists and layouts by working in conjunction with the synthesis and physical design tools. Logical and physical changes, based on this analysis, can then be implemented to achieve the desired timing constraints.
Static timing tools are used to ensure that a design implementation (net list and layout) meet imposed timing requirements. Timing correctness could be verified using delay simulation, or dynamic timing analysis, instead, in which specific waveforms are applied to the inputs of the design and resulting waveforms are produced at all points in the design. Such methods are more accurate than static timing analysis, and because of this the delays, tests, and propagations computed by static timing analysis must generally be somewhat pessimistic, meaning that they require signals to arrive earlier (through larger setup test values) or to be held longer (through larger hold test values) than might actually be necessary for correct design operation. But complete verification through simulation requires that all possible sets of input waveforms be simulated, and the number of such sets grows exponentially with the number of design inputs, making it impossible in practice to completely verify a design. The goal of a static timing analysis method is to avoid optimism (i.e., saying that a design will operate correctly when there is some input pattern whose simulation will indicate a failure), while minimizing pessimism (i.e., requiring a signal to become stable earlier or remain stable later than would be required by the simulation of any possible input pattern. Thus one way to determine the correct setup or hold test between a pair of input signals to a gate is to simulate transitions on the input signals with a variety of different spacings (differences in arrival times), and find the minimum spacing which causes the gate to have the required output. This will be the criterion against which the invention described below is measured. In particular, a designer is often concerned with a clock signal of a synchronous digital design of an IC, which synchronizes the storage of data into storage elements such as latches or flip-flops. The data held in particular storage elements is not always required during every clock cycle, and clock gating signals can be used to turn off the clock signal to such portions of the design during selected clock cycles. This can be done for functional reasons and/or to reduce power consumption, since energy that is proportional to the capacitance of the clock net is required to cause clock transitions on the clock net. Gating the clock reduces the total capacitance being switched in any given cycle. As an example, an AND gate 140 used for clock gating is shown in FIG. 1 along with idealized clock and gate signal waveforms, which are shown in FIG. 2. In FIG. 1, the AND gate 140 outputs 120 a high signal only when the clock 100 and gate 110 signals are also at a high state. Therefore, the output 120 would have a high signal only when both the gate 110 and clock signal 100 are high during time 200. Conversely, the output 120 would be low during the time 201 when only the clock signal was high. In this example, the gate signal 110 prevents the clock signal 100 from being output 120 during time 201. This is commonly referred to as xe2x80x9cclock gatingxe2x80x9d.
When clock gating is performed, it is important that the gate signal be stable during the portion of the clock cycle during which the clock is not to control the circuit in question. Thus, an AND gate disables pulses of an active-high clock, while an OR-gate disables pulses of an active-low clock. In other words, the clock gate is required to enable the entire clock pulse to pass through, or to block the entire clock pulse. If the timing of the gate signal is off, clock xe2x80x9cclippingxe2x80x9d (shortening of an intended clock pulse) and xe2x80x9cglitchingxe2x80x9d (occurrence of a portion of an unintended clock pulse) can occur, as shown in FIG. 3. More specifically, because the gate the signal 110 is shifted later in time in FIG. 3 when compared to FIG. 2, the first clock signal 200 is shortened because the beginning portion is xe2x80x9cclippedxe2x80x9d. To the contrary, the clock signal 201 which should not have been output (should have been non-controlling) is inadvertently output to as a xe2x80x9cglitchxe2x80x9d.
This requirement on the clock gate signal is ensured through static timing analysis, in which tests are imposed between the clock and gate signals. In particular, a setup test is imposed requiring that the gate signal be stable before the clock transitions to the non-controlling state, and a hold test is imposed requiring that the gate signal be held stable until after the clock transitions to the controlling state. These tests can be performed at the inputs of the clock gate, but because the delays from the clock and gate input of the gating circuit may differ, this may not ensure proper operation. As an example, consider an AND gate, as shown in FIG. 4, wherein the delay from the gate input to the output (delta-g) 141 is larger than that from the clock input to the output (delta-c) 142, as shown in FIG. 5. Here, even though the input gate signal 110 arrives to disable the clock 100 before the clock input arrives, the delay difference within the AND circuit 140 causes a glitch to occur on the output. In other words, a glitch 500 would occur on the output 120 because the clock signal 100 was so much faster than the gate signal 110, that the high clock signal 100 would arrive at the clock output 120 before the gate signal 110 had an opportunity to prevent it.
During the IC design, CAD tools are used that deal with timing constraints present throughout the circuitry. These tools provide timing analysis of circuit net lists and layouts by working in conjunction with the logic synthesis and physical design tools. EinsTimer is such a tool that is commercially available to provide this static timing analysis, made by International Business Machines Corporation, Armonk, N.Y., USA. Aspects of this tool are discussed in IBM Technical Disclosure Bulletin, Vol. 37, No. 9, pages 433-34 (September 1994) incorporated herein by reference. Presently used clock gating tests that are performed are between an arrival time (AT) at the gate output rather than at the gate input (i.e., between ATclock+delayclock and ATgate+delaygate). In FIGS. 6A and 6B the signal arrival times and slew are represented as follows: ATclock (ATc in the drawings), ATgate (ATg in the drawings), Slewclocl (Slew c in the drawings) and Slewgate (Slew g in the drawings).
Signals are not ideal sharp edges, but instead have some non-zero slew time, which is the time between when the signal starts making a transition and when it finishes the transition, often measured from the time when 10% of the transition has occurred to the time when 90% of the transition has occurred. Because of this, these tests are done between the beginning of one transition and the end of the other (i.e., a setup test between ATClock+delayClock xe2x88x92Slewclock/2 and ATgate+delaygate+Slewgate/2, or a hold test between ATClock+delayclock+Slewclock/2 and ATgate+delaygatexe2x88x92Slewgate/2). Note that the AT values are the arrival times at the gate inputs, the delay values are the delays from the 50% signal crossing point at the input of the AND circuit to the 50% crossing point at the output of the AND circuit (600, 601), and the slew values are the times it takes for output transitions propagated from the respective inputs to complete. The 0.5 slew multiplier may be changed depending on the way in which slews are defined, for example, when slews are defined as the 10% to 90% interval, this factor is set to 0.625, as this provides a better estimate of the true beginning or end of the signal transition. Waveforms meeting such a setup test are shown in FIG. 6A. This xe2x80x9cpropagatedxe2x80x9d clock gating test mode of EinsTimer is used for timing sign-off. FIG. 6A illustrates the signal relationship required by tests in conventional timing systems. FIG. 6B illustrates the signal relationship required under particular conditions by the invention and is discussed in greater detail below.
One benefit of this approach is that no special characterization of the clock gate circuit is required to determine setup and hold test values. This feature is important since it allows the use for clock gating of arbitrary gates in a circuit library, rather than restricting gating to a set of pre-characterized clock gating circuits having predefined setup times as similarly taught in U.S. Pat. No. 5,980,092 (incorporated herein by reference). This patent teaches a method for optimizing a design that uses a gated clock structure and uses an optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate. The method of this patent also includes the use of a clock tree within a circuit design. Further, an optimization tool is used to optimize the clock tree such that the clock control signal arrives at the storage element within the predefined setup and hold times of the clock signal.
In view of the above, there is a need in timing analyzers, to safely relax the constraints on the input of a gate signal to the gating device. There is also a need to modify the current clock gating test mode to handle gating signal transitions which disable a clock (i.e., prevent a clock output transition) differently from gating signal transitions which enable a clock (i.e., allow a clock output transition). This method relaxes the constraints on the clock gating signal while still preventing clock xe2x80x9cglitchingxe2x80x9d and xe2x80x9cclippingxe2x80x9d from occurring at the output.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional timing analysis tools for designing an integrated circuit, the present invention has been devised, and it is an object of the present invention to provide a method and system for determining proper setup and hold times in gating devices.
To attain the object suggested above, there is provided, according to one aspect of the invention, a method for analyzing a gated clock design, wherein tests involving a disabling clock gating transition which never causes an output transition are treated differently from enabling clock gating transitions which allow output transitions to occur. Delays and slews are computed so that the arrival time computation that includes clock and gate signal delays produces arrival times and slews at the output, and tests between these arrival times prevent a glitch or clock clipping situation from occurring. The delays and slews are computed using a static timing analysis, which considers situations such as late and early arriving gating and clock signals. The invention may be used in any static timing analysis test to ensure that a first transition on one input of a circuit prevents the propagation of a second transition on another input of the circuit.
In one embodiment, the method determines when a first-type of signal is present on a first input to a logical gating device (the first-type of input signal inhibits the propagation to the output of the gating device of transitions on a second input of the gating device) and when a second-type of signal is present on the first input (the second-type of input signal allows the propagation to the output of the gating device of transitions on the second input of the gating device). The invention modifies the timing of sensing of the first-type of signal to sense the first-type of signal at an earlier point in time than the second-type of signal is sensed. The time at which either the first-type or second-type of signal is sensed is compared against transitions propagated to the output of the gating device from the its second input to perform setup and hold tests which determine whether or not glitching or clipping may occur at the output of the gating device.
More specifically, the first-type and second-type of signal comprise gating signals applied to the first input of the gating device controlling whether pulses on the second input of the logical gating device are propagated to the output of the gate device. The first-type of signal prevents transitions from the second input from being propagated to the output of the gating device and the second-type of signal allows the clock pulses to be propagated to the output of the gating device.
The invention performs a setup test between the gate input and the clock input of the gating device in which the gate input is the first input and the clock input is the second input. By modifying the time at which the first-type signal is sensed, the invention prevents a delay in propagation of the gate signal across the gating device from inappropriately predicting the outputting of a portion of a clock pulse. To increase the sensing timing of the first-type of signal, the invention assumes that there is no load on the output when computing the gate to output delay and/or identifies a beginning point of a transition of the output due to the first-type of signal as the sensing time of the first-type of signal. Such a setup test verifies that no glitch occurs on the gate output at the beginning of the clock pulse because a disabling gate signal (intended to prevent the propagation of the current clock pulse) arrives too late.
The invention also performs a hold test between the gate input and the clock input of the gating device, in which the clock is the first input and the gate is the second input. That is, a first-type non-controlling to controlling transition on the clock input (e.g., from high to low for an AND gating) prevents a transition on the gating device output due to a subsequent controlling to non-controlling transition (e.g., from low to high for an AND gating device) on the gate input non-controlling disables a transition. By modifying the time at which the first-type signal is sensed, the invention prevents an early transition of the gate signal from inappropriately predicting the outputting of a portion of a clock pulse. The increase in the sensing timing of the first-type of signal is accomplished as for the setup test, by assuming that there is no load on the output when computing the clock to output delay and/or identifying a beginning point of a transition of the output due to the first-type of signal as the sensing time of the first-type of signal. Such a hold test verifies that no glitch occurs on the gate output at the end of the clock pulse because an enabling gate signal (intended to allow the propagation of the following clock pulse) arrives too early.
The invention is used with a timing analyzer that approves or disapproves a circuit design from a timing standpoint. Such timing analyzers may not just strictly xe2x80x9capprovexe2x80x9d a circuit design, but instead may rate the circuit design on a graduated scale. The invention recognizes that timing constraints can be relaxed considerably when the logic circuit should block a signal (to reduce the pessimism of the circuit design). Therefore, the invention will approve the timing performance of many more circuit designs than would be approved conventionally. Similarly, the invention will give higher ratings (on the graduate scale) than will be done conventionally for the timing performance of the same circuit designs. The invention relaxes timing rules (decreases pessimism) through a number of mechanisms, such as assuming that there is no load on the gate signal and multiplying the slew by factor K to modify the signal sensing time. The invention realizes that when the logic circuit should block the clock signal, the timing analyzer only needs to observe that the beginning edge of the gate signal transition has started, to find an acceptable timing situation. Thus, the invention recognizes that the logic device (gating device) will stop the clock signal as soon as the gate signal begins to transition to what is logically a blocking (gated) situation.
Further, the invention not only approves the timing of many more circuit designs than would be approved conventionally, the invention also lets the designer know that the gating signal can arrive at a later point in time, or can begin transitioning earlier in the cycle, and still be effective. This allows the designer to change the design and make other portions of the circuit more efficient knowing that the gating signal can arrive later and still perform its intended function.